The present invention relates to a switchable analogue signal inverter.
There are certain applications where it is required to produce an output analog signal having a particular one of two opposite polarities, in order to do this it has been necessary to provide a signal capable of assuming both of these polarities and then select the desired polarity signal to pass to an output. In the case of a digital to analog converter it is generally necessary to construct it so that it is able to produce both positive and negative voltages. This means that a dual-polarity DAC has to use twice as many components and occupy a relatively large area of an integrated circuit chip as compared to a single-polarity DAC. Further, it is not always convenient to provide busses carrying positive and negative voltages particularly in the case of an integrated circuit.
Chopper type inverters are well known in the art. By way of example, U.S. Patent Specification Ser. No. 2,889,470 discloses a type of inverter in which in a first instant a first capacitor is charged by an input d.c. voltage via a chopper type inverting switch whose contact(s) are in a first position, and in a second instant, when the inverting switch has been actuated so that its contact(s) are in a second position, the charge on the first capacitor is inverted and shared with a second capacitor of much larger (seven times) capacitance. The cycle of charging the first capacitor and sharing its charge with the second capacitor is continued as long as desired. Assuming that the input d.c. voltage is contant, then the voltage across the second capacitor reaches the inverted value of the input voltage after several cycles. This is because of the sharing of charge between the first and second capacitors. Thus, such an inverter is unable to track rapid changes in input voltage. Such an inverter, with its relatively large capacitors, is also not suited for high speed switching operations and for implementation as an integrated circuit.
Also known (see British Patent Specification No. 2,038,577A) is a bipolar pulse code modulation (PCM) decoder in which in response to a polarity signal in a received PCM signal, the polarity of a single polarity voltage source is set to that it is either positive or negative. Then as each linear digit of a coded value is decoded, in a first instant a first capacitor is charged or held discharged, depending on the binary value of the digit, and in a second instant the charge on the first capacitor, if present, is shared with a second capacitor which serves as a store for the charge contributions from the first capacitor. The cycle is repeated for the remaining linear digits. Thereafter, the first capacitor is discharged, and in response to segment code digits the charge on the second capacitor is shared with the first capacitor, which is discharged so that after the last segment digit the voltage remaining on the second capacitor represents the output analog voltage. The capacitors are then discharged in readiness for the next coded value to be decoded. This again represents another example of charge sharing requiring two capacitors and their inherent delay.